View AD6459_1087049.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD6459 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1996 gsm 3 v receiver if subsystem functional block diagram bpf pll lo i q gain control fref rf AD6459 features fully compliant with standard and enhanced gsm specification C11 dbm input 1 db compression point 0 dbm input third order intercept 10 db ssb noise figure (50 v ) dc-500 mhz rf and lo bandwidths linear if amplifier linear-in-db and stable over temperature voltage gain control quadrature demodulator on-board phase-locked quadrature oscillator demodulates ifs from 5 mhz to 50 mhz low power 8 ma at midgain 2 m a sleep mode operation 2.7 v to 5.5 v operation interfaces to ad7013, ad7015 and ad6421 baseband converters 20-lead ssop general description the AD6459 is a 3 v, low power receiver if subsystem for operation at input frequencies as high as 500 mhz and ifs from 5 mhz up to 50 mhz. it is optimized for operation in gsm, dcs1800 and pcs1900 receivers. it consists of a mixer, an if amplifier, i and q demodulators, a phase-locked quadra- ture oscillator, a precise agc subsystem, and a biasing system with external power-down. the AD6459s low noise, high intercept mixer is a doubly- balanced gilbert-cell type. it has a nominal C11 dbm input- referred 1 db compression point and a 0 dbm input-referred third-order intercept. the mixer section of the AD6459 also includes a local oscillator (lo) preamplifier, which lowers the required lo drive to C16 dbm. the gain control input accepts an external gain-control voltage input from an external agc detector or a dac. it provides an 80 db gain range with 27 mv/db gain scaling. the i and q demodulators provide in-phase and quadrature baseband outputs to interface with analog devices ad7013 (is54, tetra, msat) ad7015 and ad6421 (gsm, dcs1800, pcs1900) baseband converters. an on-board quadrature vco that is externally phase-locked to the if signal drives the i and q demodulators. this locked reference signal is normally provided by an external vct cxo under the control of the radios digital processor. the AD6459 can also provide demodulation of n-psk and n-qam in many non-tdma systems when used with external analog carrier recovery systems such as the costas loop. finally, the vco can be phase-locked to a frequency that is deliberately offset from the if as in the case of a beat-frequency oscillator (bfo) resulting in the product detection of cw or ssb. the AD6459 uses supply voltages from 2.7 v to 5.5 v over the temperature range of C40 c to +85 c. operation is enabled by a cmos logical level; response time is typically < 80 m s. when disabled, the standby current is reduced to 2 m a. the AD6459 comes in a 20-pin shrink small outline (ssop) surface mount package.
C2C rev. 0 AD6459Cspecifications model AD6459ars parameter conditions min typ max units dynamic performance mixer maximum rf and lo frequency 500 mhz agc conversion gain variation 0.2 v < v gain < 2.25 v C3 to +16 db input 1 db compression point @ v gain = 0.2 v C11 dbm input third-order intercept @ v gain = 0.2 v 0 dbm ssb noise figure 1 @ z s = 50 w , f rf = 240 mhz, f lo = 229.3 mhz at C16 dbm 10 db mixer output bandwidth at mxop @ C3 db 80 mhz if amplifiers agc gain variation 0.2 v < v gain <2.25 v C13 to +46 db input referred noise ac short circuit input 3 nv/ ? hz input resistance @ v gain = 0.2 v 5 k w bandwidth @ C3 db 50 mhz i and q demodulators demodulation gain 17 db output voltage range differential, irxp, irxn, qrxp, qrxn 0.3 v p C 0.2 v output voltage common-mode level (not power supply dependent) 1.5 v output offset voltage differential, v gain = gref C150 150 mv error in quadrature differential from i to q, if = 13 mhz 1.5 3.5 degree amplitude match i to q 0.25 db i/q output bandwidth c load = 10 pf 2 mhz output resistance each pin 4.7 k w gain control total gain control range mixer + if + demod, 0.2 v < v gain <2.25 v 76 db control voltage range at gain 0.2 2.4 v gain scaling 23 27 32 mv/db gain law conformance 0.5 db bias current at gref 0.5 m a input resistance at gain 20 k w pll frequency range 5 50 mhz phase noise 0.5 degree rms acquisition time if = 19.5 mhz, using suggested filter 80 m s input drive level (fref) 100 vpos mv power-down interface logical threshold power up on logical high 1.5 v input current for logical high 75 m a turn-on response time to fully meet specifications (pll lock) 80 m s turn-off response time to 200 m a supply current 1 m s standby current 2 m a power supply supply range 2.7 5.5 v supply current @ v gain = 1.2 v 8 ma operating temperature t min to t max operation to 3.3 v minimum supply voltage C40 +85 c operation to 2.7 v minimum supply voltage C25 +85 c notes 1 including if noise and using suggested filter, at v gain = 0.2 v. specifications subject to change without notice. (@ t a = +25 8 c, v p = 3.0 v, gref = 1.2 v, unless otherwise noted)
AD6459 C3C rev. 0 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD6459 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 supply voltage vps1, vps2 to com1, com2 . . . . . +5.5 v internal power dissipation 2 . . . . . . . . . . . . . . . . . . . 600 mw operating temperature range . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature, soldering (60 sec) . . . . . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended rating conditions for extended periods may affect device reliability. 2 thermal characteristics: 20-lead ssop package: q ja = 126 c/w. ordering guide temperature package package model range description option AD6459ars C25 c to +85 c 20-pin plastic rs-20 for 2.7 v to 5.5 v ssop C40 c to +85 c for 3.3 v to 5.5 v pin descriptions pin pin label description function 1 fref frequency reference input demodulation lo input. may either be 3 v cmos input or >100 mv p-p. ac-coupled for lowest stand by current. 2 com1 common 1 ground. 3 prup power up input cmos compatible power-up control; <1.5 v = off, >1.5 v = on. 4 loip local oscillator input ac-coupled lo input. 50 mv p-p drive needed, 500 mv p-p max. 5 rflo rf low input mixer differential input. ac-coupled. 6 rfhi rf high input mixer differential input. ac-coupled. 7 com2 common 2 ground. 8 gref gain reference input high impedance input. sets gain scaling, typically 1.2 v. 9 mxop mixer output plus differential output of the mixer. see figure 22. 10 mxom mixer output minus differential output of the mixer. see figure 22. 11 ifip if input plus differential input of variable gain amplifier. ac-coupled. 12 ifim if input minus differential input of variable gain amplifier. ac-coupled. 13 gain gain control input 0.2 vC2.4 v using 3 v supply. max gain at 0.2 v. 14 qrxn q output negative differential q output. output resistance 4.7 k w . 15 qrxp q output positive differential q output. output resistance 4.7 k w . 16 irxn i output negative differential i output. output resistance 4.7 k w . 17 irxp i output positive differential i output. output resistance 4.7 k w . 18 vps2 vpos supply 2 supply voltage. 19 fltr pll loop filter series rc loop filter. connected to vps2. 20 vps1 vpos supply 1 supply voltage. pin connection 20-pin ssop (rs-20) 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) AD6459 fref irxp vps2 fltr vps1 com1 prup loip qrxn qrxp irxn rflo rfhi com2 gref mxop mxom ifip ifim gain
AD6459 C4C rev. 0 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 AD6459 fref irxp vsp2 fltr vsp1 com1 prup loip qrxn qrxp irxn rflo rfhi com2 gref mxop mxom ifip ifim gain r1 20k w vpos c1 0.1? c10 1nf r8 1k w c11 0.1? c9 10nf (bottom) c7 1nf c8 1nf r6 50 w r7 50 w vpos open r4 open r5 c13 10nf c6 1nf c5 1nf fref r9 50 w r2 50 w prup loip rfhi gref r3 50 w c12 1nf c2 1nf c4 1nf c3 1nf vpos irxp qrxn qrxp irxn gain mxop mxom ifip ifim figure 1. AD6459 characterization board 1 2 3 4 8 7 6 5 ad830 v p v n a=1 c7 0.1? v n r4 50 w i out c6 0.1? v p c5 0.1? v n r3 50 w i out c4 0.1? v p gain 1 2 3 4 8 7 6 5 ad830 v p v n a=1 fref vpos gref gref prup loip rfip mxop mxom ifip ifin irxp irxn qrxp qrxn gain AD6459 characterization board prup loip rfip fref vpos c8 0.1? v n c9 0.1? v p 1 2 3 4 8 7 6 5 ad830 v p v n a=1 r5 50 w c10 0.1? v n c11 0.1? v p 1 2 3 4 8 7 6 5 ad830 v p v n a=1 r6 50 w ifin r1 50 w c2 0.1? c3 0.1? 1 2 3 4 8 7 6 5 ad830 v p v n a=1 v n v p mxop r2 50 w figure 2. characterization test set
AD6459 C5C rev. 0 rf frequency ?db 20 6 50 450 100 ssb nf ?db 150 200 250 300 350 400 18 14 12 10 8 16 r in = 50 w , if = 13mhz r in = 50 w , if = 26mhz r in = 1k w , if = 13mhz r in = 50 w , f = 45mhz r in = 400 w , if = 13mhz figure 3. mixer noise figure vs. rf frequency rf frequency ?mhz resistance ? w 2000 800 0 50 550 100 150 200 250 300 350 400 450 500 1800 1000 600 200 1400 1200 400 1600 r shunt v gain = 2.2v c shunt v gain = 0.2v c shunt v gain = 1.0v r shunt v gain = 0.2v c shunt v gain = 2.2v 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 capacitance ?pf figure 4. mixer input impedance vs. rf frequency, v pos = 2.7 v, t a = +25 c rf frequency ?mhz 20 ?0 50 450 100 gain ?db 150 200 250 300 350 400 15 10 5 0 ? v gain = 0.2v v gain = 1.0v v gain = 2.25v figure 5. mixer conversion gain vs. rf frequency, t a = +25 c, v pos = 2.7 v, v ref = 1.2 v, f if = 26 mhz rf frequency ?mhz 20 ?0 638 10 gain ?db 14 18 22 26 30 34 15 10 5 0 ? v gain = 0.2v v gain = 1.0v v gain = 2.25v 42 46 figure 6. mixer conversion gain vs. if frequency, t a = +25 c, v pos = 2.7 v, v ref = 1.2 v, frf = 250 mhz temperature ? c 70 30 0 ?0 90 ?0 gain ?db ?0 ?0 0 10 20 30 40 50 60 70 80 60 50 20 10 40 ?0 amp/demod, v pos = 2.7v amp/demod, v pos = 5.5v mixer, v pos = 2.7v mixer, v pos = 5.5v figure 7. mixer conversion gain and if amplifier/ demodulator gain vs. temperature, v gain = 0.2 v, v ref = 1.2 v , f if = 26 mhz, f rf = 250 mhz gain voltage ?volts ? ?0 ?5 0 2.5 0.5 input 1db compression point refered to 50 w ?dbm 1 1.5 2 ?1 ?2 ?3 ?4 v pos = 5.5v t a = +85 c v pos = 5.5v t a = +25 c v pos = 2.7v t a = +25 c v pos = 2.7v t a = ?5 c v pos = 5.5v t a = ?5 c figure 8. mixer input 1 db compression point vs. v gain , v ref = 1.2 v, f rf = 250 mhz, f if = 26 mhz
AD6459 C6C rev. 0 intermediate frequency ?db 70 0 545 10 15 20 25 30 35 40 60 40 30 20 10 50 v gain = 0.2v v gain = 1.0v v gain = 1.5v v gain = 2.25v if amp/demod gain ?db figure 9. if amplifier and demodulator gain vs. frequency, t a = +25 c, v pos = 2.7 v, v ref = 1.2 v if frequency ?mhz 12000 6000 0 0 100 10 resistance ? w 20 30 40 50 60 70 80 90 10000 8000 4000 2000 r shunt, v gain = 2.2v c shunt, vgain= 1.0v r shunt, v gain = 1.0v r shunt, v gains = 0.2v c shunt, v gain = 2.2v c shunt, v gain = 0.2v 3.5 3.0 2.5 2.0 1.5 1.0 0.5 capacitance ?pf figure 10. if amplifier input impedance vs. frequency, t a = +25 c, v pos = 2.7 v, v ref = 1.2 v gain voltage ?volts input 1db compression point refered to 50 w ?dbm ? ?0 ?5 0 2.5 0.5 1 1.5 2 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 figure 11. if amplifier/demodulator input 1 db compression point vs. v gain , f if = 19.5 mhz, v ref = 1.2 v, t a = +25 c, v pos = 2.7 v gain voltage ?volts 1 0.8 0 0 2.5 0.5 1 1.5 2 0.2 ?.6 ?.8 ?.0 0.6 0.4 ?.4 ?.2 mixer error ?db if amp/demod figure 12. AD6459 gain error vs. gain control voltage, representative part fref frequency ?mhz quadrature error ?degrees 3.0 0 545 10 15 20 25 30 35 40 2.5 2.0 1.5 1.0 0.5 figure 13. demodulator quadrature error vs. f ref frequency, t a = +25 c, v pos = 2.7 v carrier frequency ?khz phase noise ?dbc ?0 ?5 ?20 0.1 10k 1 10 100 1k ?00 ?05 ?10 ?15 figure 14. pll phase noise vs. frequency, v pos = 3 v, c10 = 1 nf, f ref = 13 mhz
AD6459 C7C rev. 0 pll frequency ?mhz fltr pin voltage referenced to v pos ?volts ?.1 ?.5 555 10 15 20 25 30 35 40 45 50 ?.3 ?.5 ?.7 ?.9 ?.1 ?.3 figure 15. pll loop voltage at fltr pin (kvco) vs. frequency gain voltage ?volts ?0 input 1db compression point refered to 50 w ?dbm ?0 ?0 0.5 2.5 1.0 1.5 2.0 ?0 ?0 ?0 ?0 ?0 figure 16. system (mixer + if lc filter +if amplifier + demodulator) 1 db compression point vs. gain, t a = +25 c, v pos = 2.7 v, f if = 13 mhz, v ref = 1.2 v gain voltage ?volts ?0 ?0 0 0.5 2.5 1.0 1.5 2.0 ?0 ?0 ?0 ?0 ?0 input ip3 refered to 50 w ?dbm figure 17. system (mixer + if lc filter + i f amplifier + demodulator) ip3 vs. gain, t a = +25 c, v pos = 2.7 v, if = 13 mhz, v ref = 1.2 v gain voltage ?volts supply current ?ma 18 16 4 0 2.5 0.5 1 1.5 2 12 10 8 6 14 v pos = 2.7v, t a = +85 c v pos = 2.7v, t a = +25 c v pos = 5.5v, t a = +85 c v pos = 5.5v, t a = +25 c v pos = 5.5v, t a = ?0 c figure 18. power supply current vs. gain control voltage, v ref = 1.2 v
AD6459 C8C rev. 0 product overview the AD6459 provides most of the active circuitry required to realize a complete low power, single-conversion superhetero- dyne receiver, or the latter part of a double-conversion receiver, at input frequencies up to 500 mhz, with an if from 5 mhz to 50 mhz. the internal i/q demodulators, and their associated phase-locked loop, support a wide variety of modulation modes, including n-psk, n-qam and gmsk. a single positive supply voltage of 3 v is required (2.7 v minimum, 5.5 v maximum) at a typical supply current of 8 ma at midgain. in the following discussion, v pos will be used to denote the power supply voltage, which will be normally assumed to be 3 v. figure 20 shows the main sections of the AD6459. it consists of a variable-gain uhf mixer and a linear two-stage if strip, which together provide a calibrated voltage-controlled gain range of more than 76 db, followed by dual quadrature demodulators. these are driven by inphase and quadrature clocks that are generated by a phase-locked loop (pll), which is locked to a corrected external reference. a cmos-compatible power-down interface completes the AD6459. mixer the uhf mixer is an improved gilbert-cell design and can operate from low frequencies (it is internally dc-coupled) up to an rf input of 500 mhz. the dynamic range at the input of the mixer is determined, at the upper end, by the maximum input signal level of 90 mv (C11 dbm in 50 w between rfhi and rflo) up to which the mixer remains essentially linear, and at the lower end, by the noise level. it is customary to define the linearity of a mixer in terms of its 1 db gain-compression point and third-order intercept, wh ich for the AD6459 are C11 dbm and 0 dbm, respectively, in a 50 w system. the mixers rf input port is differential; that is, pin rflo is functionally identical to rfhi, and these nodes are internally biased. the rf port can be modeled as a parallel rc circuit as shown in figure 19. rfhi rflo c sh r sh figure 19. mixer port modeled as a parallel rc network the local oscillator (lo) input is internally biased at v p C0.8 v and must be ac coupled. the lo interface includes a preampli- fier that minimizes the drive requirements, thus simplifying the oscillator design and reducing lo leakage from the rf port. the lo requires a single-sided drive of 50 mv, or C16 dbm in a 50 w system. for operation above 300 mhz, noise figure can be improved by increasing the lo level. lc bandpass filter pll vps1 rfhi AD6459 mxop mxom ifip ifim + 0 50 4.7k w 4.7k w 4.7k w 4.7k w gain to compensation agc voltage bias circuit vps2 prup rflo loip irxp irxn fref fltr qrxp qrxn gain gref 19 20 13 14 15 16 17 18 6 7 8 1 2 3 4 5 com1 com2 9 10 11 12 figure 20. functional block diagram
AD6459 C9C rev. 0 the output of the mixer is differential. the nominal conversion gain is specified for operation into a 19.5 mhz lc if bandpass filter as shown in figure 21 and table i. the conversion gain is measured between the mixer input and the input of this filter and varies between C5 db and +15 db. mxop mxom c2 l1 c1 c1 ifip ifim figure 21. suggested if filter inserted between the mixers output port and the amplifiers input port table i. filter component values for selected frequencies frequency c1 l1 c2 13 mhz 27 pf 0.82 m h 180 pf 19.5 mhz 27 pf 0.56 m h 110 pf 26 mhz 22 pf 0.39 m h 82 pf 40 mhz 22 pf 0.12 m h 100 pf the maximum permissible signal level between mxop and mxom is determined by the maximum gain control voltage. the mixer output port, having pull-up resistors of 250 w to v pos , is shown in figure 22. mxop mxom 250 w 250 w v pos figure 22. mixer output port if amplifier most of the gain in the AD6459 is provided by the if amplifier strip, which comprises two stages. both are fully differential and each has a gain span of 26 db for the agc voltage range of 0.2 v to 2.25 v. thus, in conjunction with the variable gain of the mixer, the total gain span is 76 db. the overall if gain varies from C13 db to 45 db for the nominal agc voltage of 0.2 v to 2.25 v. maximum gain is at v gain = 0.2 v. the if input is differential, at ifip and ifim. figure 23 shows a simplified schematic of the if interface modeled as parallel rc network. the ifs small-signal bandwidth is approximately 50 mhz from ifip and ifim through the demodulator. ifhi iflo c sh r sh figure 23. if amplifier port modeled as a parallel rc network gain scaling the AD6459s overall gain, expressed in decibels, is linear with respect to the agc voltage v gain at pin gain. the gain of all sections is maximum when v gain is 0.2 v and falls off as the bias is increased to v gain = 2.25 v. the gain is independent of the power supply voltage. the gain of all stages changes simultaneously. the AD6459s gain scaling is also tempera- ture compensated. note that gain pin of the AD6459 is an input driven by an external low impedance voltage source, normally a dac, under the control of the radios digital processor. the gain-control scaling is directly proportional to the reference voltage applied to the pin gref and is independent of the power supply voltage. when this input is set to the nominal value of 1.2 v, the scale is nominally 27 mv/db (37 db/v). under these conditions, 76 db of gain range (mixer plus if) corresponds to a control voltage of 0.2 v v gain % 2.25 v. the final centering of this 2.05 v range depends on the inser- tion losses of the if filters used. pin gref can be tied to an external voltage reference (v ref ) provided, for example, by an ad1580 (1.21 v) voltage reference. when using the analog devices ad7013 (is54, tetra, and satellite receiver applications) and ad7015 or ad6421 (gsm, dcs1800, pcs1900) baseband converters, the external refer- ence may also be provided by the reference output of the baseband converters. the interface between the AD6459 and the ad6421 baseband converter is shown in figure 24. the ad7015 baseband converter provides a v r of 1.23 v. an auxil- iary dac in the ad7015 can be used to generate the agc voltage. since it uses the same reference voltage, the numerical input to this dac provides an accurate rssi value in digital form, no longer requiring the reference voltage to have high absolute accuracy. AD6459 irxp irxn qrxp qrxp gref gain fref ad6421 100pf 100pf 100pf 100pf 0.1? 160 w 1nf vctcxo irxp irxp irxp irxn brefout brefcap agc dac afc dac figure 24. interfacing the AD6459 to the ad6421 baseband converter
AD6459 C10C rev. 0 i/q demodulators both demodulators (i and q) receive their inputs internally from the if amplifiers. each demodulator comprises a full-wave synchronous detector followed by an 8 mhz, two-pole low-pass filter, producing differential outputs at pins irxp and irxn, and qrxp and qrxn . using the i and q demodulators for ifs above 50 mhz is precluded by the 5 mhz to 50 mhz range of the pll used in the demodulator section. the i and q outputs are differential and can swing up to 2.2 v p-p at the low supply voltage of 2.7 v. they are nominally centered at 1.5 v, independent of power supply. they can therefore directly drive the rx adcs in the ad7015 baseband converter, which require an amplitude of 1.23 v to fully load them when driven by a differential signal. the conversion gain of the i and q demodulators is 17 db. for ifs of less than 8 mhz, the on-chip low-pass filters (8 mhz cutoff) do not adequately attenuate the if or feedthrough products; thus, the maximum input voltage must be limited to allow sufficient headroom at the i and q outputs for not only the desired baseband signal but also the unattenuated higher- order demodulation products. these products can be removed by an external low-pass filter. a simple 1-pole rc filter with its corner above the modulation bandwidth is sufficient to attenu- ate undesired outputs. the design of the rc filter is eased by the 4.7 k w resistor integrated at each i and q output pin. phase-locked loop the demodulators are driven by quadrature signals that are provided by a variable-frequency quadrature oscillator (vfqo), phase-locked to a reference signal applied to pin fref. when this signal is at the if, inphase and quadrature baseband outputs are generated at the i output (irxp and irxn) and q output (qrxp and qrxn), respectively. the quadrature accuracy of this vfqo is typically within 1.5 at 19.5 mhz. a simplified diagram of the fref input is shown in figure 25. fref 20k w 5k w 50? ptat v pos 5k w figure 25. simplified schematic of the fref interface the vfqo operates from 5 mhz to 50 mhz and is controlled by the voltage between vpos and fltr. in normal operation a series rc network, forming the pll loop filter, is connected from fltr to v pos . the use of an integral sample-hold system ensures that the frequency-control voltage on pin f ltr remains held during power-down, so reacquisition of the carrier occurs in less than 80 m s. in practice, the probability of a phase mismatch at power-up is high, so the worst case linear settling period to full lock needs to be considered in making filter choices. this is typically < 80 m s for a quadrature phase error of 3 at an if of 19.5 mhz. note that the vfqo always provides quadrature between its own i and q outputs, but the phasing between it and the reference carrier will swing around the final value during the plls settling time. bias system the AD6459 operates from a single supply (v pos ) usually 3 v, at a typical supply current of 8 ma at midgain and t a = +25 c, corresponding to a power consumption of 24 mw. any voltage from 2.7 v to 5.5 v may be used. the bias system includes a fast-acting active high cmos- compatible power-up switch, allowing the part to idle at 2 m a when disabled. biasing is generally proportional-to-absolute- temperature (ptat) to ensure stable gain with temperature. other special biasing techniques are used to ensure very accurate gain, stable over the full temperature range. using the AD6459 in this section, we will focus on a few areas of special impor- tance and include a few general application tips. as with any wideband high gain component, great care is needed in pc board layout. the location of the particular grounding points must be considered with due regard to the possibility of unwanted signal coupling. the high sensitivity of the AD6459 leads to the possibility that unwanted local em signals may have an effect on the perfor- mance. during system development, carefully-shielded test assemblies should be used. the best solution is to use a fully enclosed box enclosing all components with the minimum number of needed signal connectors (rf, lo, i and q outputs) in miniature coax form. gain distribution as with all receivers, the most critical decisions in effectively using the AD6459 relate to the partitioning of gain between the various subsections (mixer, if amplifier/demodulator) and the placement of filters to achieve the highest overall signal-to-noise ratio and lowest intermodulation distortion. figure 26 shows an example of the main rf/if signal path at maximum and minimum signal levels. signal level in dbm ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 mixer conversion gain 3db filter gain if gain demod. conv. gain i q constant baseband output 35mv ?6dbm ?6dbm ?9dbm ?6dbm ?9dbm ?9dbm ?2dbm ?9dbm ?2dbm ?5dbm ?9dbm ?5dbm ?9dbm if input 250 mhz figure 26. signal levels and gain, showing 76 db typical and 80 db maximum range in an example application
AD6459 C11C rev. 0 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 AD6459 fref irxp vps2 fltr vps1 com1 prup loip qrxn qrxp irxn rflo rfhi com2 gref mxop mxom ifip ifim gain r1 20k w vpos c1 0.1? c10 1nf r8 1k w c11 0.1? c9 10nf fref r9 50 w r2 50 w loip rfhi gref r3 50 w c12 1nf c4 1nf c7 1nf vpos irxp qrxn qrxp irxn gain c2 1nf c3 short c5 0.1? jumper vpos r6 24.9k w r7 16.9k w l3 short c16 22pf c15 110pf l2 0.56? prup gnd gref l4 short c17 22pf figure 27. evaluation board as received with 19.5 mhz filter table ii. AD6459 evaluation board input and output connection reference connector approximate designation type description coupling signal level comments rfhi sma rf input ac C11 dbm max input is terminated in 50 w loip sma lo input ac 500 mv p-p max input is terminated in 50 w fref sma demodulator reference ac 100 mv p-p min input is terminated input in 50 w mxop sma mixer output na na not connected for unbalanced output use xfmr ifip sma if input na na not connected for unbalanced output use xfmr j1 jumper on-board gref bias dc 0.4 v pos two resistors divider gref j2-1 external reference input dc 1.2 v dc g ain scaling reference from external adc gain j2-2 gain bias input dc 0.2 v to 2.4 v dc maw gain at 0.2 v qrxn j2-3 q-negative output dcC2 mhz na z series = 4.7 k w qrxp j2-4 q-positive output dcC2 mhz na z series = 4.7 k w irxn j2-5 i-negative output dc-2 mhz na z series = 4.7 k w irxp j2-6 i-positive output dc-2 mhz na z series = 4.7 k w vpos j2-7 power supply dc 2.7 v to 5.5 v supply voltage positive input prup j2-8 power up dc-2 mhz cmos if left unconnected, board is active gnd j2-j9 ground dc 0 v na gnd j2-10 ground dc 0 v na
AD6459 C12C rev. 0 c2204C12C10/96 printed in u.s.a. AD6459 evaluation board the AD6459 evaluation board (figure 27) consists of a AD6459, ground plane, i/o connectors, and a 19.5 mhz band pass filter. the rf, lo and fref ports are terminated in 50 w to provide a broadband match or external signal generators. the board provides sma connectors for the rf, lo, demodu- lator reference, mixer output and if input signals. the mxop and ifip connectors are left unconnected and are provided as a testing convenience. footprints for broadband matching trans- formers and matching components are also provided to aid in stage breakout testing. the remaining low frequency signals, including the i and q interface, bias and power connections are made via a dual row pin header that acts as an interface connector located along the edges of the board. an on-board gain-reference 1.2 v biasing option is provided via a single jumper, j1. the evaluation board will not function without this jumper unless an external bias gref is provided from an external reference that is normally provided by the associated adc. outline dimensions dimensions shown in inches and (mm). 20 11 10 1 0.295 (7.50) 0.271 (6.90) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8 0 full path configuration as received, the board is configured for full-path evaluation from rfhi to the i and q outputs. the one-pole lc resonant circuit provided represents a simple, yet balanced, if bandpass filtering approach. the filter supplied is centered at 19.5 mhz, a common gsm intermediate frequency. table i highlights the filter component values for other if frequencies. rfhi and rflo are true differential inputs, however for testing conve- nience, the rflo terminal of the AD6459 is ac referenced to ground on the evaluation board. the gain bias input, which is bypassed with a 10 nf capacitor, is brought out to the interface connector. the prup input is provided with a 20 k w pull up resistor to v pos that activates the board. the four differential i and q outputs are brought out uncondi- tioned, directly to the interface connector. a high impedance, high bandwidth fet-type probe should be used when measur- ing the i and q ports. excessive capacitive or resistive loading of these ports will severely limit the video bandwidth and signal swing. the demodulator pll filter installed on the evaluation board (r8, c10) can accommodate the full vfqo lock range specified.

▲Up To Search▲

Price & Availability of AD6459

	To Download AD6459 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .